
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:01:36 05/06/2011
-- Design Name:   ram
-- Module Name:   C:/Documents and Settings/Usuario/Mis documentos/Uni/Quinto/AIC/proyecto-manhattan-2/arquitectura/Interfaz/data/interfaz_mem/ram_tb.vhd
-- Project Name:  interfaz_mem
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ram
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT puerto
	PORT(
		acc : IN std_logic_vector(7 downto 0);
		is_in : 	 IN std_logic_vector(7 downto 0);
		is_out : IN std_logic_vector(7 downto 0);
		proc_state : in (execute, mem);
      port_cyc_o : out  STD_LOGIC;
      por_stb_o : out  STD_LOGIC;
      port_we_o : out  STD_LOGIC;
      port_ack_i : in  STD_LOGIC;
      port_addr_o : out  std_logic_vector(7 downto 0);
		);
	END COMPONENT;

	--Inputs
	SIGNAL is_in :  std_logic := '0';
	SIGNAL is_out :  std_logic := '1';
	SIGNAL proc_state :  (execute, mem);

	--Outputs
	

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: puerto PORT MAP(
		acc => acc,
		is_in => is_in,
		is_out => is_out,
		proc_state => proc_state,
		port_cyc_o => port_cyc_o,
		port_stb_o => port_stb_o,
		port_we_o => port_we_o,
		port_ack_i => port_ack_i,
		port_addr_o => port_addr_o
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;
		is_in <= '0';
		is_out <= '1';
		proc_state <= execute;
		wait for 100 ns;
		proc_state <= mem;
		port_ack_i <='1';
		
		is_in <= '1';
		is_out <= '0';
		proc_state <= execute;
		wait for 100 ns;
		proc_state <= mem;
		port_ack_i <='1';
		wait; -- will wait forever
	END PROCESS;

END;


  --  Test Bench Statements
     tb : PROCESS
     BEGIN

        wait for 100 ns; -- wait until global set/reset completes

        -- Add user defined stimulus here

        wait; -- will wait forever
     END PROCESS tb;
  --  End Test Bench 

  END;
